EV-ADF4196SD1Z 查看數據表（PDF） - Analog Devices
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EV-ADF4196SD1Z Datasheet PDF : 28 Pages
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ADF4196
POWER-DOWN REGISTER (R5) BIT MAP
PD
DIFF AMP
CONTROL
BITS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
F5 F4 F3 F2 F1 C3 (1) C2 (0) C1 (1)
Data Sheet
F1 COUNTER RESET
0 NORMAL OPERATION
1 COUNTER RESET
CHARGE PUMP
F2 3-STATE
0 NORMAL OPERATION
1 3-STATE ENABLED
CHARGE PUMP
F3 POWER-DOWN
0 DISABLED
1 ENABLED
DIFF AMP
F5 F4 POWER-DOWN
0 0 DISABLED
1 1 ENABLED
Figure 34. Bit Map for Register R5
R5, the power-down register, can be used to power down the PLL
and differential amplifier sections. After power is initially applied,
Register R5 must be programmed to clear the power-down bits.
Then, before the ADF4196 comes out of power-down, the R2,
R1, and R0 registers must be programmed.
Control Bits
Register R5 is selected with C3, C2, and C1 set to 1, 0, 1.
The charge pump is powered down with its outputs in
three-state mode.
The digital lock detect circuitry is reset.
The RFIN input is debiased.
The reference input buffer circuitry is disabled.
The serial interface remains active and capable of loading
and latching data.
Power-Down Differential Amplifier
For normal operation, set Bit DB5 to 0, followed by a write to R0.
When the DB7 and DB6 bits are set to 1, the differential
amplifier is put into power-down. When DB7 and DB6 are set
to 0, normal operation resumes.
Power-Down Charge Pump
CP Three-State
When the CP three-state bit is set to 1, the charge pump outputs
enter three-state. Setting the CP three-state bit to 0 enables the
charge pump outputs.
Setting Bit DB5 to 1 activates a charge pump power-down, and
the following events occur:
All active dc current paths are removed, except for the
differential amplifier.
The R and N divider counters are forced to their load state
conditions.
Counter Reset
When the counter reset bit is set to 1, the counters are held in reset.
For normal operation, set this bit to 0, followed by a write to R0.
Rev. D | Page 20 of 28
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