EV-ADF4196SD1Z 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

比赛名单

EV-ADF4196SD1Z

Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer

Analog Devices 

ADF4196

Data Sheet

FUNCTION REGISTER (R3) LATCH MAP

RESERVED

CONTROL

BITS

DB15 DB14 DB13 DB12 DB11 DB10 DB9

0

0

0

0

0

0

0

DB8

0

DB7

0

DB6

1

DB5

F3

DB4

1

DB3 DB2 DB1 DB0

F1 C3 (0) C2 (1) C1 (1)

F1 PFD POLARITY

0 NEGATIVE

1 POSITIVE

F3 CPO GND

0 CPO/CPO GND

1 NORMAL

Figure 32. Bit Map for Register R3

R3, the function register, needs to be programmed only during

the initialization sequence (see Table 9).

Control Bits

PFD Polarity

Set the PFD polarity bit to 1 for positive polarity, and set it to 0

for negative polarity.

Register R3 is selected with C3, C2, and C1 set to 0, 1, 1.

Reserved Bits

CPO GND

When the CPO GND bit is low, the charge pump outputs are

internally pulled to ground. This is invoked during the initiali-

zation sequence to discharge the loop filter capacitors. For

normal operation, this bit should be set to 1.

Program the DB15 to DB6 reserved bits to a hexadecimal code of

0x001, and set the DB4 reserved bit to 1.

Rev. D | Page 18 of 28

Share Link: