CP667 数据手册 ( 数据表 ) - Central Semiconductor
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CP667
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Central Semiconductor
PROCESS DETAILS
Process EPITAXIAL PLANAR
Die Size 31 x 31 MILS
Die Thickness 9.0 MILS
Base Bonding Pad Area 5.9 x 11.8 MILS
Emitter Bonding Pad Area 6.5 x 13.8 MILS
Top Side Metalization Al - 30,000Å
Back Side Metalization Au - 15,000Å
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Small Signal Transistor PNP - Saturated Switch Transistor Chip ( Rev : 2002 )
Central Semiconductor
Small Signal Transistor NPN - Saturated Switch Transistor Chip ( Rev : 2002 )
Central Semiconductor
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