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V54C3128404V 数据手册 ( 数据表 ) - Mosel Vitelic Corporation

V54C3128804V image

零件编号
V54C3128404V

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生产厂家
Mosel-Vitelic
Mosel Vitelic Corporation  Mosel-Vitelic

Description
The V54C3128(16/80/40)4V(BGA) is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16, 4 banks x 4Mbit x 8, or 4 banks x 8Mbit x 4. The V54C3128(16/80/40)4V(BGA) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.


FEATUREs
■ 4 banks x 2Mbit x 16 organization
■ 4 banks x 4Mbit x 8 organization
■ 4 banks x 8Mbit x 4 organization
■ High speed data transfer rates up to 166 MHz
■ Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 3
■ Programmable Wrap Sequence: Sequential or Interleave
■ Programmable Burst Length:
   1, 2, 4, 8 for Sequential Type
   1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 60 Pin WBGA
■ LVTTL Interface
■ Single +3.3 V ±0.3 V Power Supply

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零件编号
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