Description
The V54C365404VD(L) is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 4. The V54C365404VD(L) achieves high speed data transfer rates up to 143 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock
All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

FEATUREs
■ 4 banks x 4Mbit x 4 organization
■ High speed data transfer rates up to 143 MHz
■ Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge
■ Single Pulsed RAS Interface
■ Data Mask for Read/Write Control
■ Four Banks controlled by BA0 & BA1
■ Programmable CAS Latency: 2, 3
■ Programmable Wrap Sequence: Sequential or Interleave
■ Programmable Burst Length:
   1, 2, 4, 8 and full page for Sequential Type
   1, 2, 4, 8 for Interleave Type
■ Multiple Burst Read with Single Write Operation
■ Automatic and Controlled Precharge Command
■ Random Column Address every CLK (1-N Rule)
■ Suspend Mode and Power Down Mode
■ Auto Refresh and Self Refresh
■ Refresh Interval: 4096 cycles/64 ms
■ Available in 54 Pin 400 mil TSOP-II
■ LVTTL Interface
■ Single +3.3 V ±0.3 V Power Supply