L3GD20 查看數據表（PDF） - STMicroelectronics
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L3GD20 Datasheet PDF : 44 Pages
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L3GD20
Mechanical and electrical specifications
2.4
Communication interface characteristics
2.4.1
SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Table 6. SPI slave timing values
Symbol
Parameter
Value(1)
Min
Max
Unit
tc(SPC)
fc(SPC)
tsu(CS)
th(CS)
tsu(SI)
th(SI)
tv(SO)
th(SO)
tdis(SO)
SPI clock cycle
SPI clock frequency
CS setup time
CS hold time
SDI input setup time
SDI input hold time
SDO valid output time
SDO output hold time
SDO output disable time
100
ns
10
MHz
5
8
5
15
ns
50
6
50
1. Values are guaranteed at a 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not
tested in production.
Figure 3. SPI slave timing diagram (a)
&6
63&
WVX &6
WVX 6,
WK 6,
WF 63&
6',
06%,1
WY 62
6'2
06%287
WK 62
WK &6
/6%,1
WGLV 62
/6%287
!-V
a. Measurement points are at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output port.
Doc ID 022116 Rev 1
11/44
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