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L3GD20 查看數據表(PDF) - STMicroelectronics

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L3GD20 Datasheet PDF : 44 Pages
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Digital main blocks
L3GD20
4.2.4
Bypass-to-stream mode
In Bypass-to-stream mode, the FIFO begins operating in Bypass mode and once a trigger
event occurs (related to INT1_CFG (30h) register events), the FIFO starts operating in
Stream mode. Refer to Figure 10 below.
Figure 10. Bypass-to-stream mode
xi,yi,zi
x0
yi0
z0
Empty
x1
y1
z1
x2
y2
z2
x31
y31
z31
xi,yi,zi
x0
y0
z0
x1
y1
z1
x2
y2
z2
x30
y30
z30
x31
y31
z31
4.2.5
Bypass mode
Stream mode
Trigger event
AM07235v1
Stream-to-FIFO mode
In Stream-to-FIFO mode, data from yaw, pitch and roll measurement is stored in the FIFO. A
watermark interrupt can be enabled on pin DRDY/INT2 by setting the I2_WTM bit in
CTRL_REG3 (22h) in order to be raised when the FIFO is filled to the level specified in the
WTM4:0 bits of FIFO_CTRL_REG (2Eh). The FIFO continues filling until it is full (32 slots of
16-bit data for yaw, pitch and roll). When full, the FIFO discards the older data as the new
data arrives. Once a trigger event occurs (related to INT1_CFG (30h) register events), the
FIFO starts operating in FIFO mode. Refer to Figure 11 below.
Figure 11. Trigger stream mode
xi,yi,zi
x0
y0
z0
x1
y1
z1
x2
y2
z2
x30
y30
z30
x31
y31
z31
xi,yi,zi
x0
yi0
z0
x1
y1
z1
x2
y2
z2
x31
y31
z31
20/44
Stream Mode
Trigger event
FIFO Mode
Doc ID 022116 Rev 1
AM07236v1

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