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M37640E8FP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Mitsumi 

Ver 1.4

MITSUBISHI MICROCOMPUTERS

7640 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

1.14.5.7 Port 8

Port 8 is an 8-bit general purpose I/O port that can be

configured to access special second functions. The

port can be set up in any configuration in all three pro-

cessor modes.

Port P80

This pin is multiplexed with the SIO SRDY signal and

the UART2 TxD signal. When UART2 is in transmit

mode, the pin acts as the TxD output signal. When

the pin is not being used as the UART2 TxD output

and bit 4 of the SIO control register 1 (SIOCON1) is a

“1”, the port acts as the SIO SRDY output signal. If

during this function, the SIO is configured in slave

mode, this pin acts as a slave input from a master.

See section 1.18 for more SIO information.

Port P81

This pin is multiplexed with the SIO SCLK signal and

the UART2 RxD signal. When UART2 is in receive

mode, the pin acts as the RxD input signal. When the

pin is not being used as the UART2 RxD input and bit

2 of the SIO control register 1 (SIOCON1) is a “1”, the

port acts as the SIO SCLK signal. In this mode a “1”

in bit 6 of SIOCON1 configures the pin to output

SCLK whereas a “0” configures the pin to input SCLK.

Port P82

This pin is multiplexed with the SIO SRxD signal and

the UART2 CTS signal. When bit 5 of the UART2

control register (U2CON) is a “1”, the port acts as the

CTS input signal. When the pin is not being used as

the UART2 CTS input and bit 2 of the SIO control reg-

ister 2 (SIOCON2) is a “1”, the port acts as the SIO

SRxD input signal.

Port P83

This pin is multiplexed with the SIO STxD signal and

the UART2 RTS signal. When bit 6 of the UART2

control register (U2CON) is a “1”, the port acts as the

RTS output signal. When the pin is not being used as

the UART2 RTS output and bit 3 of the SIO control

register 1 (SIOCON1) is a “1”, the port acts as the

SIO STxD output signal.

Port P80 SRDY Output Selection Bit

UART2 Transmit Control Bit

Data Bus

Direction Register

Port Latch

SIO Slave mode selection bit

Port P82 SIO Receive Enable Bit

UART2 CTS Enable Bit

Direction Register

Data Bus

Port Latch

SIO Ready Output

UART2 TxD Output

Port P81 SIO Clock Selection Bit

SIO Port Selection Bit

UART2 receive control Bit

Direction Register

Data Bus

Port Latch

SIO Slave mode selection bit

SIO slave control

UART2 receive control bit

Port P83

P-Channel Output Disable Bit

Transmit Complete Signal

SIO Port Selection Bit

SIO Clock Selection Bit

UART2 RTS Enable Bit

Direction Register

Data Bus

Port Latch

SIO Clock Output

UART2 receive control bit

UART2 RxD input

SIO clock input

Fig. 1.20. Port P80, P81, P82, P83 Block Diagram

SIO TxD Output

UART2 RTS Output

UART2 CTS Enable Bit

UART2 CTS input

SIO RxD input

23

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