MP8830AE 查看數據表（PDF） - Exar Corporation

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MP8830AE

Triple 10-bit High Speed Analog-to-Digital Converter with Digitally Controlled References

Exar Corporation 

MP8830

THEORY OF OPERATION

The MP8830 is composed of three ADC converters with dy-

namic gain and offset control along with their associated analog

and digital support circuitry. The three converters are intended

to be used in a simultaneous sampling configuration. The only

external circuits required are a reference and reference buffer

amp.

The ADC gain and offset DAC inputs, ADC output data, and

the AIN sampling time are related to the four clock inputs, CVL,

AENL, BENL and CENL.

In applications which require rejecting a bias level from the

analog input, a zero clamp is provided for each channel. With

the addition of a buffer input amp and blocking capacitor, this

function rejects the bias present during DCL = 0 time on the ana-

log input.

ADC calibration or test can be performed using the built-in

VCAL / AIN MUX which will switch the ADC AIN from the channel

input voltage, AAN, BAN, CAN to VCAL.

A fast mode is provided, where only the four ADC MSBs are

produced while the remaining data is set to 00(hex).

To simplify board layout, a data pass-through configuration is

provided to allow bi-directional communication between the

ADC data port and the 10 MSBs of the DAC I/O port.

ADC System Overall Sequence

The following section describes the events which take place

during one conversion cycle (Figures 1-4). Assume at power up,

or in the previous cycle, that the values for the gains and offsets

needed for this sample set have been loaded into the first DAC

registers. This data is loaded into the second registers for all

three channels on the rising edge of CVL. AIN tracking for all

channels is also started after tAP delay. Note that the AENL,

BENL and CENL were at “1” states.

At the falling edge of AENL, the channel A gain and offset

data for the next cycle is loaded into the channel A first DAC reg-

ister. The analog input sample for all three channels is taken at

the rising edge of AENL after tAP delay.

At the falling edge of BENL, the channel B gain and offset

data for the next cycle is loaded into the channel B first DAC reg-

ister. The MSB comparators are also enabled at this time. At the

rising edge of BENL, the MSB value is latched, and the range for

the LSBs is selected. Note that the gain and offset DAC must be

settled by this time in order for the MSB value to be correct (t7 +

t4 + t1 ensure this.)

At the falling edge of CENL, the channel C gain and offset

data for the next cycle is loaded into the channel C first DAC reg-

ister. The LSB comparators are also enabled at this time. At the

rising edge of CENL, the LSB value is latched.

During the time (t9) when CENL =1 and CVL = 0, the MSB

data is corrected (if necessary) and then propagated along with

the LSB data to the ADC outputs. On the rising edge of CVL,

channel A data is enabled at the output port.

Since the actual ADC samples are taken at the rising edge of

AENL after tAP delay, this period of time is the most sensitive to

transition noise from digital components. Keep all transitions

outside of the t18, t19 digital quiet time window around the AENL

rising edge. Since the ADC output bus will change states at the

rising edge of CVL, the time from CVL rising to AENL rising is

important. The delay from CVL rising to channel A valid on the

ADC bus is t8. This requires that AENL rising edge must not oc-

cur until at least t8 after CVL rising.

CVL Functions

CVL rising edge performs three functions. The first is to up-

date the gain and offset DACs from their respective first regis-

ters simultaneously. The second function is to initiate the sam-

ple window. The third function is to latch the results of the pre-

vious conversions into the ADC output register.

The A channel ADC data is presented at the ADC data port

after CVL rising edge. CVL falling edge does not change any

internal state.

DAC Data Port Operation

DAC data is loaded first into an input register and then loaded

into the DAC register.

The input register allows sequential loading of the next con-

version settings for all the channels through the 15-bit DAC data

bus while the ADC data is being clocked out of the ADC data

port. The second register allows for simultaneous updating of all

channels at the beginning of the analog sample period. This tim-

ing gives the ADC reference levels adequate time to settle be-

fore being used to convert the sampled AIN. Note that the DAC

data must be presented at each cycle, since there is no provision

for holding DAC data after each cycle.

At power up, the DAC states should be set for the first sam-

ple’s required gain and offset settings. This is accomplished by

setting CVL = 1, and cycling each of the AENL, BENL, and

CENL clocks from their 1 to 0 to 1 states sequentially with each

channel’s respective data present at the DAC data port.

Rev. 1.00

10

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