MP8830
TIMING DIAGRAMS
AAN
BAN
CAN
CVL
AENL
BENL
CENL
DCL
ACLP
BCLP
CCLP
0.1%
t10
t6
t7
t4
t12
t1
t1
t3
t9
t1
Figure 1. Clock Timing for Convert Mode
t16
t16
Figure 2. DC Clamp Operation
Channel A output data enabled on this edge
All DAC outputs update on this edge
CVL
tAP
Sample N Window
tAP
t9
AENL
BENL
t18 t19
CENL
AD(0-9)
OUTPUTS
t8
C Data (N-2)
t8
A Data (N-1)
DA (0-14)
INPUTS
t5
t2
A (N+1)
t5
t2
B (N+1)
t8
B Data (N-1)
C Data (N-1)
t5
t2
C (N+1)
Figure 3. DAC Input and ADC Output Timing for Normal Convert Operation (CREN = 0)
Rev. 1.00
8