MP8830AE 查看數據表（PDF） - Exar Corporation

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MP8830AE

Triple 10-bit High Speed Analog-to-Digital Converter with Digitally Controlled References

Exar Corporation 

MP8830

Parameter

Symbol

Min

Typ

Max Units Test Conditions/Comments

3-State Leakage

IOZ

–10

Digital Timing Specifications2

10 µA

In pass-through mode

For testing, rise time = fall time =

10 ns. Output loading = 60 pF except for

AD0-AD9 for which loading is 40 pF. Rise

and fall times faster than 5 ns should be

avoided.

AENL, BENL, CENL

t1

125

ns

Pulse Width

D/A Data Hold Time

t2

20

ns

BENL Rising Edge to CENL Rising t3

270

ns

Edge

AENL Rising Edge to CVL Falling

t4

30

ns

Edge

D/A Data Setup Time

Analog Input Hold Time

t5

20

t6

20

CVL Rising Edge to AENL Rising

t7

230

Edge

ns

ns

Measured as part of analog feedthrough test.

Note, ttapmax < t4min + t6min.

ns

A/D Data Enable Time

t8

40 ns

CVL to Channel A data.

BENL to Channel B data.

CENL to Channel C data.

CENL Rising Edge to CVL Rising

t9

40

ns

Edge

Analog Input Settled to 0.1%

t10

50

ns

Assumes the sample is taken at the rising

edge of AENL.

A/D Data Hold Time

Aperture Delay

t11

20

ns

tAP

20

40 ns

Analog sampling window delay from CVL ris-

ing (↑) edge (start) or AENL rising (↑) edge

(end).

CVL Falling Edge to BENL Rising

t12

180

ns

Edge

Delay from CD5-14 to AD0-9 with

t13

CREN=1

50 ns

Delay from AD0-9 to CD5-14 with

t14

CREN = 1

50 ns

Delay from DCL Falling Edge to

t15

Clamp on.

40 ns

External analog clamp voltage settling de-

pends on external circuitry.

Delay from DCL Rising Edge to

t16

Clamp off.

40 ns

External analog clamp voltage settling de-

pends on external circuitry.

Time for AD0-9 and CD5-14 to switch t17

0

from normal operation to pass

through mode or vise versa (i.e. bus

contention).

40 ns

User should stop driving the bus before

changing the mode and data will not be valid

for 40 ns after a change of mode.

Digital Quiet Time

t18

15

ns

This quiet time is necessary to reduce digital

crosstalk during the critical sampling time.

The accuracy of each conversion may be cor-

rupted due to digital noise on the board during

this period.

Digital Quiet Time

t19

40

ns

This quiet time is necessary to reduce digital

crosstalk during the critical sampling time.

The accuracy of each conversion may be cor-

rupted due to digital noise on the board during

this period.

Notes

1 Production testing performanced at 25°C.

2 Not production tested.

Rev. 1.00

6

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