XC858CA
Electrical Parameters
Table 43 shows the timing of the external data memory write cycle.
Table 43 External Data Memory Write Timing (Operating Conditions apply)
Parameter
Symbol
Limit Values
Min.
Max.
Unit Test
Conditions
WR pulse width
t1
Address valid to WR
t2
Data valid to WR transition t3
Data setup before WR
t4
Data hold after WR
t5
CC fCCLK - 10
-
CC 2*fCCLK - 7
-
SR fCCLK - 5
-
SR 9*fCCLK - 13 -
SR 6*fCCLK - 3 -
ns
1)
ns
1)
ns
1)
ns
1)
ns
1)
1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.
Addresses
WR
D[7:0]
DATA ADDRESS
t2
t1
t3
t5
VALID
t4
Figure 40 External Data Memory Write Cycle
Data Sheet
109
V1.0, 2010-03