SAF-XC858CA-16FFI5V 查看數據表（PDF） - Infineon Technologies

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SAF-XC858CA-16FFI5V

8-Bit Single-Chip Microcontroller

Infineon Technologies 

XC858CA

Electrical Parameters

4.3.7 JTAG Timing

Table 45 provides the characteristics of the JTAG timing in the XC858.

Table 45 TCK Clock Timing (Operating Conditions apply; CL = 50 pF)

Parameter

Symbol

Limits Unit Test Conditions

min max

TCK clock period

tTCK SR 50

-

ns

1)

TCK high time

t1 SR 20

-

ns

1)

TCK low time

t2 SR 20

-

ns

1)

TCK clock rise time

t3 SR -

4

ns

1)

TCK clock fall time

t4 SR -

4

ns

1)

1) Not all parameters are 100% tested, but are verified by design/characterization and test correlation.

TCK

0.5 V DDP

t1

t2

tTCK

t4

t3

0.9 V DDP

0.1 V DDP

Figure 42 TCK Clock Timing

Table 46 JTAG Timing (Operating Conditions apply; CL = 50 pF)

Parameter

Symbol

Limits

Unit Test Conditions

TMS setup to TCK

min max

t1 SR 8

-

ns

1)

TMS hold to TCK

t2 SR 0

-

ns

1)

TDI setup to TCK

t1 SR 8

-

ns

1)

TDI hold to TCK

t2 SR 4

-

ns

1)

TDO valid output from TCK t3 CC -

24

ns

1)

Data Sheet

111

V1.0, 2010-03

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