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PLL103-07 数据手册 ( 数据表 ) - PhaseLink Corporation

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零件编号
PLL103-07

产品描述 (功能)

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7 Pages

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130.7 kB

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PLL
PhaseLink Corporation PLL

DESCRIPTIONS
The PLL103-07 is designed as a 2.5V buffer to distribute high-speed clocks in PC applications. The device has 12 outputs. These outputs can be configured to support 2 DDR DIMMs. The PLL103-07 can be used in conjunction with the PLL202-04 or similar clock synthesizer for the VIA Pro 266 chipset.


FEATURES
• Generates 12-output buffers from one input.
• Supports VIA Pro266 DDR chipset.
• Supports up to 2 DDR DIMMS.
• Supports up to 400MHz DDR, SDRAMS.
• One additional output for feedback.
• 6 differential clock distribution.
• Less than 5ns delay.
• Skew between any outputs is less than 100 ps.
• 2.5V Supply range.
• Available in 28-pin SSOP.

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零件编号
产品描述 (功能)
PDF
生产厂家
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