HS-80C86RH 查看數據表（PDF） - Intersil

零件编号

产品描述 (功能)

比赛名单

HS-80C86RH

Radiation Hardened 16-Bit CMOS Microprocessor

Intersil 

Waveforms (Continued)

CLK

TCLAV

QS0, QS1

S2, S1, S0 (EXCEPT HALT)

TCLAV

BHE/S7, A19/S6-A16/S3

TSVLH

TCLLH

ALE (82C88 OUTPUT)

NOTE 55

RDY

(HS-82C85RH INPUT)

HS-80C86RH

T1

TCLCL

TCHCL

T2

TCH1CH2

TCHSV

TCLDV

TCLAX

BHE, A19-A16

TCHLL

TR1VCL

TCLR1X

TRYLCL

T3

T4

TCL2CL1 TW

TCLCH

TCLSH

(SEE NOTE 58)

TCLAV

S7-S3

READY (HS-80C86RH INPUT)

TCLAX

TRYHSH

TRYHCH

TCHRYX

READ CYCLE

TCLAV

AD15-AD0

RD

DT/R

TCHDTL

AD15-AD0

TAZRL

TCLAZ

TDVCL

TCLDX1

DATA IN

TCLRH

TRHAV

TCLRL

TRLRH

TCHDTH

82C88

OUTPUTS

SEE NOTES

55, 56

MRDC OR IORC

TCLML

TCVNV

TCLMH

DEN

TCVNX

NOTES:

FIGURE 3. BUS TIMING - MAXIMUM MODE SYSTEM

51. All signals switch between VOH and VOL unless otherwise specified.

52. RDY is sampled near the end of T2, T3, TW to determine if TW machines states are to be inserted.

53. Cascade address is valid between first and second INTA cycle.

54. Two INTA cycles run back-to-back. The HS-80C86RH local ADDR/DATA bus is inactive during both INTA cycles. Control for pointer address is

shown for the second INTA cycle.

55. Signals at HS-82C85RH or 82C88 are shown for reference only.

56. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high

82C88 CEN.

57. All timing measurements are made at 1.5V unless otherwise noted.

58. Status inactive in state just prior to T4.

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