HS-80C86RH 查看數據表（PDF） - Intersil

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HS-80C86RH

Radiation Hardened 16-Bit CMOS Microprocessor

Intersil 

HS-80C86RH

Waveforms (Continued)

CLK

TINVCH (SEE NOTE)

NMI

INTR SIGNAL

TEST

NOTE: Setup Requirements for asynchronous signals only to

guarantee recognition at next CLK.

FIGURE 5. ASYNCHRONOUS SIGNAL RECOGNITION

CLK

TCLAV

ANY CLK CYCLE

TCLAV

ANY CLK CYCLE

LOCK

FIGURE 6. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ONLY)

CLK

TCLGH

RQ/GT

TCLCL

PREVIOUS GRANT

AD15-AD0

ANY

CLK

CYCLE

≥ 0-CLK

CYCLES

TCLGL

TCLGH

TGVCH

TCHGX

PULSE 1

COPROCESSOR

RQ

HS-80C86RH

PULSE 2

HS-80C86RH

GT

TCLAZ

PULSE 3

COPROCESSOR

RELEASE

RD, LOCK

BHE/S7, A19/S6-A16/S3

S2, S1, S0

TCHSZ

(SEE NOTE) TCHSV

NOTE: The coprocessor may not drive the buses outside the region shown without risking contention.

FIGURE 7. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

CLK

HOLD

HLDA

AD15-AD0

≥ 1CLK

CYCLE

THVCH

80C86

1 OR 2

CYCLES

THVCH

TCLHAV

TCLAZ

COPROCESSOR

TCLHAV

80C86

BHE/S7, A19/S6-A16/S3

RD, WR, M/IO, DT/R, DEN

TCHSZ

FIGURE 8. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

15

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