HS-80C86RH 查看數據表（PDF） - Intersil
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HS-80C86RH Datasheet PDF : 29 Pages
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HS-80C86RH
Functional Description
Static Operation
All HS-80C86RH circuitry is of static design. Internal
registers, counters and latches are static and require no
refresh as with dynamic circuit design. This eliminates the
minimum operating frequency restriction placed on other
microprocessors. The CMOS HS-80C86RH can operate
from DC to 5MHz. The processor clock may be stopped in
either state (HIGH/LOW) and held there indefinitely. This
type of operation is especially useful for system debug or
power critical applications.
The HS-80C86RH can be single stepped using only the CPU
clock. This state can be maintained as long as is necessary.
Single step clock operation allows simple interface circuitry to
provide critical information for bringing up your system.
Static design also allows very low frequency operation
(down to DC). In a power critical situation, this can provide
extremely low power operation since HS-80C86RH power
dissipation is directly related to operating frequency. As the
system frequency is reduced, so is the operating power until,
ultimately, at a DC input frequency, the HS-80C86RH power
requirement is the standby current, (500µA maximum).
Internal Architecture
The internal functions of the HS-80C86RH processor are
partitioned logically into two processing units. The first is the
Bus Interface Unit (BIU) and the second is the Execution
Unit (EU) as shown in the CPU functional diagram.
These units can interact directly but for the most part
perform as separate asynchronous operational processors.
The bus interface unit provides the functions related to
instruction fetching and queuing, operand fetch and store,
and address relocation. This unit also provides the basic bus
control. The overlap of instruction pre-fetching provided by
this unit serves to increase processor performance through
improved bus bandwidth utilization. Up to 6 bytes of the
instruction stream can be queued while waiting for decoding
and execution.
The instruction stream queuing mechanism allows the BlU to
keep the memory utilized very efficiently. Whenever there is
space for at least 2 bytes in the queue, the BlU will attempt a
word fetch memory cycle. This greatly reduces “dead-time”
on the memory bus. The queue acts as a First-In-First-Out
(FlFO) buffer, from which the EU extracts instruction bytes
as required. If the queue is empty (following a branch
instruction, for example), the first byte into the queue
immediately becomes available to the EU.
The execution unit receives pre-fetched instructions from the
BlU queue and provides un-relocated operand addresses to
the BlU. Memory operands are passed through the BlU for
processing by the EU, which passes results to the BlU for
storage.
Memory Organization
The processor provides a 20-bit address to memory, which
locates the byte being referenced. The memory is
organized as a linear array of up to 1 million bytes,
addressed as 00000(H) to FFFFF(H). The memory is
logically divided into code, data, extra and stack segments
of up to 64K bytes each, with each segment falling on 16
byte boundaries. (See Figure 9).
FFFFFH
64K BIT
SEGMENT
REGISTER FILE
CS
SS
DS
ES
+ OFFSET
CODE SEGMENT
XXXXOH
STACK SEGMENT
DATA SEGMENT
EXTRA SEGMENT
00000H
FIGURE 9. HS-80C86RH MEMORY ORGANIZATION
TABLE 1.
DEFAULT
TYPE OF MEMORY SEGMENT
REFERENCE
BASE
ALTERNATE
SEGMENT
BASE
OFFSET
Instruction Fetch
CS
None
IP
Stack Operation
SS
None
SP
Variable
DS
(Except Following)
CS, ES, SS Effective
Address
String Source
DS
CS, ES, SS SI
String Destination
ES
None
DI
BP Used as Base
Register
SS
CS, DS, ES Effective
Address
All memory references are made relative to base addresses
contained in high speed segment registers. The segment
types were chosen based on the addressing needs of
programs. The segment register to be selected is
automatically chosen according to the specific rules of
Table 1. All information in one segment type share the same
logical attributes (e.g., code or data). By structuring memory
16
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