HS-80C86RH 查看數據表（PDF） - Intersil
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HS-80C86RH Datasheet PDF : 29 Pages
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HS-80C86RH
Status bits S0, S1 and S2 are used by the bus controller, in
maximum mode, to identify the type of bus transaction
according to Table 2.
TABLE 2.
S2
S1
S0
CHARACTERISTICS
0
0
0 Interrupt Acknowledge
0
0
1 Read I/O Port
0
1
0 Write I/O Port
0
1
1 Halt
1
0
0 Instruction Fetch
1
0
1 Read Data from Memory
1
1
0 Write Data to Memory
1
1
1 Passive (no bus cycle)
Status bits S3 through S7 are time multiplexed with high order
address bits and the BHE signal, and are therefore valid
during T2 through T4. S3 and S4 indicate which segment
register (see Instruction Set Description) was used for this bus
cycle in forming the address, according to Table 3.
TABLE 3.
S4
S3
CHARACTERISTICS
0 (Low) 0 Alternate Data (extra segment)
0
1 Stack
1 (High) 0 Code or None
1
1 Data
S5 is a reflection of the PSW interrupt enable bit. S6 is
always zero and S7 is a spare status bit.
I/O Addressing
In the HS-80C86RH, I/O operations can address up to a
maximum of 64K I/O byte registers or 32K I/O word
registers. The I/O address appears in the same format as
the memory address on bus lines A15-A0. The address lines
A19-A16 are zero in I/O operations. The variable I/O
instructions which use register DX as a pointer have full
address capability while the direct I/O instructions directly
address one or two of the 256 I/O byte locations in page 0 of
the I/O address space.
I/O ports are addressed in the same manner as memory
locations. Even addressed bytes are transferred on the
D7-D0 bus lines and odd addressed bytes on D15-D8. Care
must be taken to ensure that each register within an 8-bit
peripheral located on the lower portion of the bus be
addressed as even.
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