CDB6403 查看數據表（PDF） - Cirrus Logic
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CDB6403 Datasheet PDF : 54 Pages
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CS6403
The CS6403 requires one sample time to effect a
write to a control register. As a result, a control-
word write should not be followed in the next
control word with a read to the same control
word. There should be at least one intervening
sample time prior to the next control word read
to that control word.
Control Register Definitions
The CS6403 has four control registers that are
accessible via the SSI, which allow a user to
monitor and control the behavior of the CS6403.
Note that these registers are accessible only in
Mode 2 (16-bit). Some visibility and control is
provided by the GPIN and GPOUT pins (see
PIN DESCRIPTIONS).
The following table defines the four registers ac-
cessible by the serial interface in 16-bit modes.
These registers are accessed by setting b15 high.
The state of b14 indicates whether the register
access operation is a read (high) or a write (low).
Bits b13 and b12 together address the register as
follows:
b13 : b12
00
01
10
11
Register
SSI_CR0
SSI_CR1
SSI_CR2
(reserved)
Note that CR0 is different from the other three
control registers, in that CR0 is read by the
CS6403 CPU only at reset. Also, CR0 may be
changed via a serial control operation only im-
mediately after the control word "0x8400" is
written to the CS6403 (which puts the CS6403
into "sleep" mode).
Input Companded Audio Word (8-bit)
b7
b6
b5
b4
Output Companded Audio Word (8-bit)
b7
b6
b5
b4
Input Companded Audio Word (16-bit)
0
0
0
0
0
0
0
0
Output Companded Audio Word (16-bit)
b7 b6 b5 b4 b3 b2 b1 b0
Input Linear Audio Word (16-bit)
0 b14 b13 b12 b11 b10 b9 b8
Output Linear Audio Word (16-bit)
b15 b14 b13 b12 b11 b10 b9 b8
Input Control Word (16-bit)
1 RNW a1 a0 b11 b10 b9 b8
Output Control Word (16-bit)
1 RNW a1 a0 b11 b10 b9 b8
b3
b3
b7 b6
0
0
b7 b6
b7 b6
b7 b6
b7 b6
b2
b2
b5 b4
0
0
b5 b4
b5 b4
b5 b4
b5 b4
b1
b1
b3 b2
0
0
b3 b2
b3 b2
b3 b2
b3 b2
b0
b0
b1 b0
0
0
b1 b0
b1 b0
b1 b0
b1 b0
Table 3. Audio and Control Data Format for Mode 2
DS192PP6
17
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