CDB6403 查看數據表（PDF） - Cirrus Logic
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CDB6403 Datasheet PDF : 54 Pages
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CS6403
Register SSI_CR0
B11 B10
B9
B8
B7
B6
B5
RST SLP AGCRD NECD FHPD NHPD CE
0
0
0
0
0
0
0
B4
PED
0
B3
GBC1
1
B2
B1
B0
GBC0 AECB1 AECB0
0
1
0
This register is read from the SSI by the CPU only upon exit from Reset and Sleep. This register is
cleared at reset except for B3-B0 (see below).
BIT
RST
NAME
Reset
SLP
Sleep
AGCRD
AGC-Rescale Disable
NECD
FHPD
NHPD
CE
NEC Disable
FE_IN High-Pass
Disable
NE_IN High-Pass Disable
Companding Enable
PED
Pre-Emphasis Disable
"R" indicates value after Reset
VALUE
0R
1
0R
1
0R
1
0R
1
0R
1
0R
1
0R
1
0R
1
FUNCTION
Normal operation.
Control registers and RAMs are cleared, and then
control constants are loaded into Data RAM. SSI is
still operational, though writes to any control bit
except RST are ignored.
Normal operation.
The CPU and AFP on the CS6403 are powered
down. Control registers and RAMs are unaffected.
Serial Data transactions that occur during power
down are transferred directly between the SSI and
the codec, bypassing the CPU. As a result, echo is
passed uncancelled.
SPKROUT volume is scaled to full-scale after
peak-limiter.
SPKROUT signal is peak-limited version of far-end
input.
10 ms of the available 64 ms of EC taps are
allocated by default to network echo cancellation.
No taps are allocated to network echo cancellation.
A high-pass filter ((1-D)/(1-0.75D)) is inserted in the
far-end input signal path.
This filter is bypassed.
A high-pass filter ((1-D)/(1-0.75D)) is inserted in the
near-end input signal path.
This filter is bypassed.
Data in 16-bit data modes is linear (i.e., not
companded).
b15 is still used as the steering bit, but if b15=0, the
least significant 8 bits are companded data.
A pre-emphasis filter is placed before the input to the
adaptive filter.
This filter is bypassed.
DS192PP6
19
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