Functional Description
The CY7C1339G SRAM integrates 128 K × 32 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (CE1), depth-expansion chip enables (CE2 and CE3), burst control inputs (ADSC, ADSP, and ADV), write enables (BW[A:D], and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and the ZZ pin.

FEATUREs
■ Registered inputs and outputs for pipelined operation
■ 128 K × 32 common I/O architecture
■ 3.3 V core power supply (VDD)
■ 2.5 V/3.3 V I/O power supply (VDDQ)
■ Fast clock-to-output times
    ❐ 4.0 ns (for 133-MHz device)
■ Provide high-performance 3-1-1-1 access rate
■ User-selectable burst counter supporting Intel® Pentium® interleaved or linear burst sequences
■ Separate processor and controller address strobes
■ Synchronous self-timed writes
■ Asynchronous output enable
■ Available in Pb-free 100-pin TQFP package
■ “ZZ” sleep mode option